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Selecting an FPGA Carrier Board: FMC, PCIe and I/O Planning

Stripline Engineering · · 8 min read

A carrier board decision looks like a parts decision but behaves like an architecture decision: change it in month six and the schedule notices. The selection questions worth asking are about interfaces and headroom, not logic-cell counts.

Start from the data, not the FPGA

Write down every producer and consumer: ADC lanes in, DMA to host, storage, control. Then do the two sums that kill projects when skipped:

Pin budget. An FMC LPC site gives you 68 single-ended user pins (34 LVDS pairs). HPC doubles that and adds transceiver pairs. A 14-bit ADC pair at 250 MSPS in parallel LVDS eats most of an LPC site by itself. Check the mezzanine's pinout against the carrier's connected pins, because carriers routinely wire only a subset.

Bandwidth budget. PCIe Gen2 x1 moves ~400 MB/s of real payload after protocol overhead; Gen3 x4 moves ~3.2 GB/s. Two 250 MSPS × 14-bit channels produce 875 MB/s sustained. Lane count is a decision you make at carrier selection, not at bring-up.

Memory is usually the real constraint

Buffering, waveform capture and DSP working sets all want DRAM bandwidth. A single 16-bit DDR3-800 interface offers ~3.2 GB/s theoretical. Call it half that sustained with a real access pattern. If your capture depth or frame rate maths lands anywhere near that number, you need a carrier with a wider or faster memory interface, and no amount of HDL heroics changes it.

The checklist that predicts bring-up pain

  • Reference design quality. Constraints files, a DMA example that compiles on the current toolchain, and a driver that ships signed. Ask whether the reference design is versioned with checksums, so the one you download is the one that was tested.
  • Clocking. Is there a clean, low-jitter clock to the transceiver quads and an external reference input? Retrofitting one is misery.
  • Power sequencing and monitoring done on-board, not left to you.
  • JTAG that coexists with your debugger and the vendor tools.
  • Mechanical: mounting holes, height envelopes with the mezzanine installed, airflow direction.

If the project is a radio, look for a platform that puts the transceivers and the FPGA on one board: our Spectra-4 SDR pairs two AD9361 transceivers with a Zynq-7035 for four transmit and four receive chains.

When to go custom

Volume above a few hundred units a year, a form-factor constraint, or a BOM cost target usually tips the maths toward a custom carrier, which is work we take on, reference design included.